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Group: Forum Members
Last Login: 23/02/2012 12:35:58
Posts: 16,
Visits: 48
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Hi - first post here,
I am trying to describe a counter which accepts an address and
increments by 1 each cycle. The problem is that the counter always
starts at 0 even when reset is '0'. I have attached the code below. Can
anybody see where I am going wrong? I thought that by assigning the
value 'a' to 'temp_address' in the process that it would work as
expected.
Any feedback welcome - thanks.
entity c1_new_address is
generic (n: integer := 14);
port (a: in std_logic_vector((n-1) downto 0);
clk, reset: in std_logic;
w: out std_logic_vector((n-1) downto 0));
end c1_new_address;
architecture Behavioral of c1_new_address is
signal temp_address: std_logic_vector((n-1) downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
temp_address <= (others => '0');
elsif rising_edge(clk) then
temp_address <= a;
temp_address <= conv_std_logic_vector((conv_integer(temp_address) +
1), 14);
end if;
w <= temp_address;
end process;
end Behavioral;
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Group: Forum Members
Last Login: 30/03/2012 17:11:20
Posts: 1,
Visits: 4
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Hi first reply.
vhdl process is not sequential, it is parallel, it only apllies at the end of the process.
So the:
temp_address <= a;
is being ignored.
Also you probably want:
temp_address <= conv_std_logic_vector((conv_integer(temp_address) +
1), 14);
to have the generic not 14. I would have chosen something a bit longer to than "n".
Easier then to search for.
So the question is, do you want it to load the a input then count, just after reset?
If so add a control bit.
---- something like below, probably with mistakes.
entity c1_new_address is
generic (n: integer := 14);
port (a: in std_logic_vector((n-1) downto 0);
clk, reset: in std_logic;
w: out std_logic_vector((n-1) downto 0));
end c1_new_address;
architecture Behavioral of c1_new_address is
signal temp_address: std_logic_vector((n-1) downto 0);
signal start_count: std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
temp_address <= (others => '0');
start_count <= "0";
elsif rising_edge(clk) then
start_count <="1";
if (start_count == "0") then
temp_address <= a;
else
temp_address <= conv_std_logic_vector((conv_integer(temp_address) +
1), n);
end if;
end if;
w <= temp_address;
end process;
end Behavioral;
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Group: Forum Members
Last Login: 23/02/2012 12:35:58
Posts: 16,
Visits: 48
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Thanks mhutt! That's a great help!
Will let you know how it goes....
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Group: Forum Members
Last Login: 25/04/2012 07:50:39
Posts: 1,
Visits: 2
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Can vector be changed at the Temp Address? Or it must be same for all the resultant record set?
Edited: 30/04/2012 17:24:12 by
Admin
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